Optimized Real-time simulation for VSC-HVDC bipolar scheme with physical control replica in the loop

Voltage Direct Current (HVDC) bipolar scheme with physical control replica in the loop. The

VSC-HVDC bipolar technology is one considered in the InterOPERA project which aims to achieve interoperability of multi-vendor HVDC grids connecting offshore wind farms. To test this interoperability, a real-time simulation demonstrator will contain physical control and protection replicas from each HVDC vendors. The Hardware-In-the-Loop (HIL) setup of each replica involving the Electro-Magnetic Transient (EMT) modelling of HVDC converters is quite challenging in terms of performance in such time-constrained simulations. The EMT solution method used for the simulation is based on the solution of sparse linear systems at each time-point. The sparse network matrix is factorized into LDU factors. The LDU form, consisting of triangular L and U matrices and a diagonal matrix D, simplifies the solution process. Repetitive commutations from HVDC converters slow down this solution process as factorization should be redone from the updated linear sparse system. Otherwise, for parallelization, no natural propagation delay is available to decouple the solution without any loss of accuracy. Sparse solver solution methods based on partial refactorization technique or free-delay parallelization technique such as the Compensation Method are tested on a HIL

VSC-HVDC bipolar setup in Static synchronous compensator (STATCOM) mode. Several test scenarios validated the performance gains.