A Review of Practical Approaches to Dielectric Valve Terminal AC-DC Tests for Modular Multi-level Voltage Sourced Converters Incorporating Rapid Discharge Circuits

Method 1 (M1) and Method 2 (M2)—used to assess dielectric performance and voltage balancing of a VSC Valve design under normal and fault conditions. This paper evaluates their limitations for Valve designs incorporating Rapid Discharge Resistor circuits (RDRs) and proposes guidance for selecting test objects, methods, and conditions within a hybrid M1–M2 approach.

Dielectric testing has two objectives: verifying over-voltage withstand capability during faults and assessing steady-state voltage grading and partial discharge behaviour. Both are challenging for Valve designs using electronic RDR circuits, which IEC 62501 does not fully address.

M1 energizes individual Valve Submodules (VSMs) and is preferred by some HVDC system owners, but it cannot meet both test objectives for RDR-equipped Valves. The active operation protection provided by the RDR circuit prevents the voltage from reaching the required withstand level. In addition, it does not consider Valve designs using high-voltage switching regulator powered gate electronics and having RDR-based blocked-Valve balancing, as both switch randomly and introduce interference that compromises partial discharge measurements.

M2 combines routine withstand and partial discharge tests on key individual VSM components, and dielectric type test on the Valve structure using external grading circuits and shorted VSMs.

This paper analyses voltage distribution and stresses across operating and fault conditions for

Valve designs incorporating rapid discharge resistor circuits and recommends a combined M1–

M2 strategy, using M1 on a smaller test object as part of operational type tests to validate active transient over-voltage protection and blocked-state balancing, and using M2 on a Valve tower structure as part of dielectric test to verify the overall dielectric performance.